Echelon Series 6000 Chip databook Manual de usuario

005-0230-01BProvides detailed specifications on the electrical inter-faces, mechanical interfaces, and operating environment characteristics for the F

Two 16-Bit Timer/Counters ... 100 Summary of the Available I/O Objects ...

Avoiding Magnetic Field Interference All transformer-based transceivers are vulnerable to stray magnetic fields that can interfere with the transform

Summary and Testing Results Table 26 summarizes the results of the immunity and RF testing for a typical LONWORKS application based on an FT 6000 Sma

5 Network Cabling and Connections for FT Devices This chapter describes the network connections and cable types supported for FT devices. Series 60

Network Connection For a TP/FT-10 channel, the network connection (from the NETP and NETN pins) is polarity insensitive. Therefore, either of the t

Figure 38. Star Topology Figure 39. Loop, or Ring, Topology Series 6000 Chip Data Book 93

Figure 40. Mixed Topology In the event that the limits for the number of transceivers or total wire distance are exceeded, then one FTT physical lay

procedures for TP/FT-10 channels, be sure to include the TP/FT-10 system specifications and, based upon the cable used, the appropriate transmission

Cable Type Maximum Device-to-Device Distance (Meters) Maximum Total Wire Length (Meters) J-Y(ST)Y 2x2x0.8 320 500 ANSI/TIA/EIA Category 5 / 6 250

Ca and Cb are typically aluminum-electrolytic type for improved longevity in the presence of ESD. Be sure to observe their polarity. Grounding Shiel

I/O and Network Connections ... 157 BOM for Example Schematic ...

6 Input/Output Interfaces for the Series 6000 This chapter provides an overview of the I/O models that are available for Series 6000 devices. See t

Overview Echelon’s Neuron Chips and Smart Transceivers connect to application-specific external hardware through 11 or 12 I/O pins, named IO0-IO11.

Figure 43. Timer/Counter Circuits No I/O pins are dedicated to timer/counter functions. If, for example, Timer/Counter 1 is used for input signals o

• Timer/Counter I/O Models use a timer/counter circuit in the Neuron Chip or Smart Transceiver. Each Neuron Chip and each Smart Transceiver has two

I/O Model Applicable I/O Pins Total Pins per Object Input/Output Value Bit Output1 IO0 – IO11 1 0, 1 binary data Byte Input IO0 – IO7 8 0 – 255

Table 31. Summary of the Serial I/O Models I/O Model Applicable I/O Pins Total Pins per Object Input/Output Value Bitshift Input Any adjacent pair (

Table 32. Summary of the Timer/Counter Input Models I/O Model Applicable I/O Pins Total Pins per Object Input/Output Value Dualslope Input IO0, IO1

I/O Model Applicable I/O Pins Total Pins per Object Input/Output Value Triac Output2 IO0, IO1 + (one of IO4 – IO7) 2 Delay of output pulse with res

addition to the parallel or muxbus object for the following device types: PL 3120-E4, PL 3150, or PL 3170. For Series 6000 devices, you can also de

Parallel I/OTIMER/COUNTER INPUT MODELSSERIAL I/OMODELSPARALLEL I/O MODELSDIRECT I/O MODELSBit Input, Bit OutputByte Input, Byte OutputLeveldetect Inp

Example: The following I/O object types can be combined for a Neuron Chip or Smart Transceiver: • 1 parallel I/O object type (on IO_0..IO10) OR

source and sink capability. If your I/O circuitry has higher current requirements, you can add external driver circuitry (for example, using a Fairc

• Events on the I/O pins for the input timer/counter functions are accurately measured, and a value returned to a register, regardless of the state

7 Programming Considerations This chapter describes software tools for creating applications that run on Series 6000 devices. Series 6000 Chip Da

Application Program Development You can perform initial development and test for Neuron C applications using the IzoT NodeBuilder Development Tool.

the available system clock rates for your device. However, the recommended internal clock speed is 80MHz. The reason is that transient code must be

SNMP Support The Series 6000 chip supports SNMP V1. The following are the commands and objects that are implemented. Supported Commands SNMP Get S

Name: interfaces.ifOutOctets ID: 1.3.6.1.2.1.2.2.1.16 The total number of octets transmitted out of the interface, including framing characters.

1 Introduction This chapter introduces the Series 6000 of products, LONWORKS networks, and free topology networking. Series 6000 Chip Data Book

access_nv() access_alias() update_nv() update_alias() Both the NV and Alias configuration structures can be referenced using macros named NV_STRUCT

A Series 6000 Design Checklists This appendix includes a set of checklists, including chip connections, power supplies, PCB layout, and network cabl

Checklist 1: Series 6000 Chip Connections This checklist applies to all Series 6000 chips, including FT 6000 Smart Transceivers and Neuron 6000 Proce

Check When Complete Item Description CC10 Capacitors (30 pF 5% 50V NPO) are placed at the XIN and XOUT pins (23 and 24), as described in Clock R

Checklist 2: FT 6000 Smart Transceiver Connections This checklist applies to FT 6000 Smart Transceivers. Check When Complete Item Description FC

Checklist 3: Neuron 6000 Processor Connections This checklist applies to Neuron 6000 Processors. Check When Complete Item Description NC1 All i

Checklist 4: Power Supply This checklist applies to all Series 6000 chips, including FT 6000 Smart Transceivers and Neuron 6000 Processors. Check W

Checklist 5: Device PCB Layout This checklist applies to all Series 6000 chips, including FT 6000 Smart Transceivers and Neuron 6000 Processors. Chec

Checklist 6: Network Cabling and Termination This checklist applies to FT 6000 Smart Transceivers. Check When Complete Item Description NT1 The

Checklist 7: Device Programming This checklist applies to all Series 6000 chips, including FT 6000 Smart Transceivers and Neuron 6000 Processors. Che

Product Family Overview Echelon designed the original Neuron Chip as a system-on-a-chip semiconductor device to provide intelligence and networking c

B Qualified TP/FT-10 Cable Specifications This appendix describes generic cable specifications for cables that Echelon has qualified to work with TP/

Introduction This appendix documents generic cable specifications for cables that Echelon has qualified to work with TP/FT-10 channels. Specific ve

Notes: • AWG: American wire gauge. See ASTM B258 - 02(2008) Standard Specification for Standard Nominal Diameters and Cross-Sectional Areas of AWG

Table 37. Impedance Characteristics Frequency Impedance (Ohms) 772 kHz 102 ±15% (87-117) 1.0 MHz 100 ±15% (85-115) 4.0 MHz 100 ±15% (85-115) 8.0

Table 39. Worst-Pair Near-End Crosstalk (dB) Minimums Specification Value (dB) 772 kHz 58 1.0 MHz 56 4.0 MHz 47 8.0 MHz 42 10.0 MHz 41 16.0 MHz

Table 41. Attenuation and Propagation Delay Characteristics Characteristic Maximum Condition Attenuation 20 kHz 64 kHz 78 kHz 156 kHz 256 kHz 512 k

C FT-X3 Communications Transformer This appendix describes the FT-X3 Communications Transformer, including its pinout, electrical connections, and p

Transformer Pinout Figure 49 shows the pinout for the FT-X3 Communications Transformer and the equivalent electrical schematic. The FT-X3 Communica

Transformer Electrical Connections Figure 48 shows the electrical connections for the FT-X3 Communications Transformer. The NETP and NETN signals re

Introduction to LONWORKS Networks In almost every industry, there is a trend away from proprietary control schemes and centralized systems. The migr

D3ABAV9913BAV99D4B13D3BBAV993 2BAV99D4A32+C622 uF63V12+C722 uF63V12VR1470V12JP1HDR2 200 MIL R/A21NETBNETA Figure 49. FT Network Electrical Connection

Notes for the figure: • Maintain a minimum distance of 2 mm between a routed trace and any of the transformer pads or traces. This distance is espe

D Handling and Manufacturing Guidelines This appendix describes guidelines for handling and manufacturing devices that use the Neuron 6000 Processor

Application Considerations This section describes application considerations for design and manufacturing of LONWORKS devices. Termination of Unused

• Connecting individual unused I/O pins directly to GND or to VDD. This method is not recommended in case of software error and because of the poss

causes leakage or shorts. Often secondary damage occurs after an initial zap failure causes a short. • Latch-up refers to a usually catastrophic c

Figure 54. Digital I/O Electrostatic Discharge Design Guidelines There are many ways to deal with ESD, including: • Divert or limit energy from p

• Use short, low-inductance, traces for the analog circuitry to reduce inductive, capacitive, and radio frequency (RF) noise sensitivities. • Use s

Hazardous Substances (RoHS) Directive (2002/95/EC), thus their profiles use the lead-free assembly, with a peak temperature Tp of 260 ºC. Soldering S

Echelon’s implementation of the ISO/IEC 14908-1 Control Network Protocol is called the LonTalk protocol. Echelon provides implementations of the Lon

because they appear as intermittent failures or as degraded performance. Static damage can often increase leakage currents. CMOS devices are not imm

d. Completed assemblies should be placed in antistatic containers prior to being moved to subsequent stations. Figure 55. Networks for Minimizing

Figure 56. Typical Manufacturing Work Station Notes for Figure 56: 1. 1/16-inch conductive sheet stock covering bench-top work area. 2. Ground str

7. Equipment specifications should alert users to the presence of CMOS devices and require familiarization with this specification prior to performi

• VDD3V3 pins: 8, 18, 29, 30, 31, 41 • VDD1V8 pins: 6, 16, 27, 44 Recommendation: Add an additional 1.0 μF (6.3 V, 10%, X7R) capacitor to pin 27

Reference Part C12 1.0 µF for pin 27 VOUT1V8 C16 0.01 µF across pins 25 and 26 (VDDPLL and GNDPLL) C17 0.1 µF for pin 16 VDD1V8 C18 0.1 µF for p

E Example Schematic This appendix provides an example schematic for an FT 6000 Smart Transceiver, with associated non-volatile memory, communications

Example Schematic This appendix provides an example schematic for an FT 6000 Smart Transceiver. The example schematics are based on the FT 6000 Ev

Memory Interface Connections Figure 61 shows the connections for the serial memory interface. The figure shows connections to a a flash memory devic

Series 6000 based field devices are capable of running multiple protocols (LonTalk, LonTalk/IP, BACnet/IP, SNMP, ICMP with UDP sockets available) wit

CP2_TXRST-NETASVC-D214BAV9975V31 2NETBNETAIO11NETBIO0VDD5XR 8JP101HDR2 200MIL R/A21D101BBAV9975V3 2+C10222uFALUM ELEC63V12D101ABAV9975V13D213BAV9975V

Reference Designator Value C6 1.0 µF C101, C102 22 µF D1, D2, D3, D4, D101, D102, D213, D214, D215, D216 BAV99 L1, L2 150 Ω R6, R7, R8, R13 49.9

F Vendor Contact Information This appendix lists contact information for many of the product vendors mentioned in this manual. 160 Index

Vendor Information This appendix lists contact information for many of the product vendors mentioned in this manual. For most of the parts listed in

BPM Microsystems Headquarters 5373 West Sam Houston Pkwy N, Suite 250 Houston, TX 77041 USA Phone: +1 713-688-4600 Toll Free (US): 800-225-2102 Fa

Emulation Technology Inc. Headquarters 2320 Walsh Avenue Building H, Suite E Santa Clara, CA 95051 USA Toll Free (US): 800-ADAPTER (800-232-7837)

Laird Technologies PLC Headquarters 100 Pall Mall London UK SW1Y 5NQ Phone: +44 (0)20 7468 4040 Fax: +44 (0)20 7839 2921 US Office 16401 Swingle

NXP Semiconductors BV Headquarters High Tech Campus 45 5656 AE Eindhoven Netherlands Phone: +31 40 27 29999 Fax: +31 40 27 43375 www.nxp.com

Plastronics Socket Company Inc. Headquarters 2601 Texas Drive Irving, Texas 75062 USA Phone: +1 972-258-2580 Toll Free (US): 800-582-5822 Fax: +1 9

Taiyo Yuden Company Ltd. Headquarters Matsumura Bldg. 6-16-20 Ueno Taito-Ku, Tokyo 110-0005 Japan Phone: 81-3-3833-5441 Fax: 81-3-3835-4754 US Of

Smart TransceiverSmart TransceiverSmart TransceiverSmart TransceiverSmart TransceiverSmart TransceiverTerminationTo Additional Free Topology DevicesS

Vishay Intertechnology Inc. Headquarters 63 Lancaster Avenue Malvern, PA 19355-2143 USA Phone: +1 402-563-6866 Fax: +1 402-563-6296 www.vishay.c

Figure 2. Typical Wiring Topologies Supported by FT Smart Transceivers This design has many advantages: • The installer is free to select the meth

Echelon, LONWORKS, LonTalk, Neuron, 3120, 3150, LNS, FTXL, Izot, ShortStack, and the Echelon logo are trademarks of Echelon Corporation that may be r

Key Features of Series 6000 Chips Series 6000 chips include the following key features: • Provide a high performance Neuron Core, with internal sys

Specification Summaries The following sections summarize the specifications for FT 6000 Smart Transceivers and Neuron 6000 Processors. Specificatio

Description Specification Reflow soldering temperature profile Refer to Joint Industry Standard document IPC/JEDEC J-STD-020D.1 (March 2008) Peak r

Specification Summary for Neuron 6000 Processors Table 6 summarizes the specifications for the Neuron 6000 Processor. Table 6. Neuron 6000 Processor

2 Hardware Resources This chapter provides an overview of the hardware resources for an FT 6000 Smart Transceiver and a Neuron 6000 Processor,

Series 6000 Architecture The main components of the architecture for a Series 6000 chip, as shown in Figure 3 include: • CPUs — a Series 6000 chip i

Clock, Reset, and ServiceSerial Memory InterfaceRAM(64K x 8)I/OComm PortNET CPUTransformerortransceiverNVM (SPI)ROM(16K x 8)JTAGAPP CPUIRQ CPUMAC CPU

symbol NEXT refers to the next element in the data stack, which is determined by contents of the location (BP+DSP) in memory, and is thus not an actu

1. Incrementing RSP 2. Moving the contents of (BP+RSP) to the low byte of the IP register 3. Incrementing RSP 4. Moving the contents of (BP+RSP)

Welcome Echelon’s FT 6000 Free Topology Smart Transceiver is the latest addition to Echelon’s FT Smart Transceiver family. The FT 6000 Smart Tran

Register Size (Bits) Contents BP 16 Address of 256-Byte Base Page DSP 8 Data Stack Pointer within Base Page RSP 8 Return Stack Pointer within

Interrupts The Series 6000 architecture provides hardware support for handling three types of interrupts: • Lowest priority: application interrupt

in the Neuron Assembly language. The Neuron C compiler can optionally produce an assembly listing, and examining this listing can help the programme

Instruction Instruction Size (Bytes) CPU Cycles Required Description CALLF 3 7 Call subroutine far Pushes two bytes to return stack. Table 9. M

Instruction Instruction Size (Bytes) CPU Cycles Required Description PUSH #literal 2 4 Push 8-bit literal value [0 to 255] PUSHPOP 1 5 Pop fro

Instruction Instruction Size (Bytes) CPU Cycles Required Description SHLA SHRA 1 2 Signed left shift TOS into carry Signed right shift TOS into ca

On-Chip Memory A Series 6000 chip has the following on-chip memory: • 16 KB of read-only memory (ROM) The ROM holds an initial system image that

System and I/ONetwork Image (shadowed to NVM)Stacks, buffers, app dataFFFFF800F000E800Application NVM (shadowed to NVM)Application DataApplication an

The memory map divides the Series 6000 chip’s physical RAM into the following types of logical memory: • System Image (0x0000 to __image_end (system

A Series 6000 chip is always the master SPI device; any external NVM devices are always slave devices. Multimaster configurations are not supported.

The memory map for a Series 6000 chip is “auto-tuned”. This means that the linker decides how to partition the RAM based upon the needs placed on i

of this area (e.g., network configuration tables). This area comprises either 2 or 4 flash sectors of 4KB each depending on the demands of the appli

• ON Semiconductor LE25U40CMC 4 M-bit 2.3V minimum SPI serial flash memory • Micron M25PX80 8 M-bit 2.3V minimum SPI serial flash memory • Macroni

2. Press and hold the device’s Reset button. If the device does not have a Reset button, connect the RST~ pin (pin 28) of the Series 6000 chip to G

failure in the device. The write-protected part of the flash contains the bootloader, active system image, and active application. JTAG Interface A

• SAMPLE/PRELOAD — samples current values, or preloads known values into the boundary-scan cells for a follow-on operation Required by the IEEE 1149

1. All parameters assume nominal supply voltage (VDD3 = 3.3 V) and operating temperature (TA between -40 ºC and +85 ºC), unless otherwise noted. 2.

Pin Assignments Although the pin assignments for the Neuron 6000 Processor and the FT 6000 Smart Transceiver are very similar, there are a few differ

Table 14. FT 6000 Smart Transceiver Pin Assignments Name Pin Number Type Description SVC~ 1 Digital I/O Service (active low) IO0 2 Digital I/O

Name Pin Number Type Description VIN3V3 29 Power 3.3 V input to internal voltage regulator VDD3V3 30 Power 3.3 V Power AVDD3V3 31 Power 3.3 V Po

SVC~IO0IO1IO2IO3VDD1V8IO4VDD3V3IO5IO6IO7IO8 VDDPLLGNDPLLVOUT1V8RST~VIN3V3VDD3V3AVDD3V3CP0AGNDCP1NCGNDIO9IO10IO11VDD1V8TRST~VDD3V3TCKTMSTDITDOXINXOUTC

Title Part Number Description Introduction to the LONWORKS Platform 078-0183-01B This manual provides an introduction to the ISO/IEC 14908 (ANSI/E

Name Pin Number Type Description IO6 10 Digital I/O IO6 for I/O Objects IO7 11 Digital I/O IO7 for I/O Objects IO8 12 Digital I/O IO8 for I/O Ob

Name Pin Number Type Description CP3 38 Comm Do Not Connect CP4 39 Comm Single-Ended Mode: Collision detect Special-Purpose Mode: Frame clock CS

FT 6000Smart TransceiverU1FT 5000SVC~1IO02IO13IO24IO35VDD1V86IO47VDD3V38IO59IO610IO711IO812IO913IO1014IO1115VDD1V816TRST~17VDD3V318TCK19TMS20TDI21TDO

FT 6000Smart TransceiverU1FT 5000SVC~1IO02IO13IO24IO35VDD1V86IO47VDD3V38IO59IO610IO711IO812IO913IO1014IO1115VDD1V816TRST~17VDD3V318TCK19TMS20TDI21TDO

FT 6000Smart TransceiverU1FT 5000SVC~1IO02IO13IO24IO35VDD1V86IO47VDD3V38IO59IO610IO711IO812IO913IO1014IO1115VDD1V816TRST~17VDD3V318TCK19TMS20TDI21TDO

VDD3R14.99k12TCK Figure 14. Connection for the JTAG TCK Pin Characteristics of the Digital Pins Series 6000 chips provide 12 bidirectional I/O pins

Notes: 1. All parameters assume nominal supply voltage (VDD3 = 3.3 V) and operating temperature (TA between –40 ºC and +85 ºC), unless otherwise not

device’s external serial non-volatile memory must be loaded with the correct communications parameters before connecting to the network. CP0CP1CP2CP3

output after transmitting the last bit. The line-code violation begins after the end of the last CRC bit, and lasts for at least 2.5 bit times. The

CP0CP1CP2CP3CP4TransmitEnableNeuron 6000 ProcessorData InputData OutputTransmit Enable OutputCollisionDetect~ InputDifferential Manchester DecoderDif

All of the Echelon product documentation is available in Adobe® PDF format. To view the PDF files, you must have a current version of the Adobe Read

Important: Transmit Enable is actively driven at all times in single-ended mode. In single-ended mode, the 8 mA driver is connected to CP1 and it i

• Beta 1 Time after Transmission = 583 cycles + Transmit Interpacket Padding + Beta 2 Slot Width • Beta 1 Time after Reception = 565 cycles + Rece

in the communications medium, or instability in the transmitting or receiving device’s input clocks. The jitter tolerance windows are expressed as f

restricted protocol that Echelon licenses for use only when the Neuron Chip and transceiver are sold as one unit. For more details, contact Echelon

Table 19. Special-Purpose Mode Transmit Status Bits Bit Flag Description 7 TX_FLAG Neuron Chip in the process of transmitting packet 6 TX_REQ_FL

2. Configuration data — Information from the Neuron Chip that tells the transceiver how it is to be set up or configured. 3. Status data — Informat

information in the data field. The Neuron Chip continues to send the status request command until it receives a frame with the RD/WR ACK bit set. Ne

Name Value Description C1, C2 56 pF, 50 V Common-mode noise immunity capacitors (for EN61000-4-6 Level 3) C3, C4 100 pF, 5% Optional center-ta

Transceiver is a 3.3 V part and the FT 3120 or FT 3150 Smart Transceiver is a 5 V part); the packages are different; and the pinouts are different.

A device based on a Series 6000 Smart Transceiver with the FT-X3 transformer can run the same applications (after they are recompiled for the FT 6000

You can purchase copies of CENELEC documents, IEC EMC standards, ISO standards, US Military Standards, and CISPR documents from the Information Handl

CP2CP1CP4CP3CP0DATA_BDATA_ACP3CP2GNDVDD5CP0CP12543976137 TXEN34 TX393832 RXNeuron 6000 Processor TPT/XF-12503.3 V Single-Ended Mode+5 VVDD3V3+3.3 V88

inputs for the connection to the Neuron 6000 Processor. A typical circuit configuration, shown in Figure 22, can support up to 32 loads. Individua

CP0CP1CP3CP2CP432 RX34 TX3837 TXEN39Neuron 6000 ProcessorLPT-11 Link Power Transceiver3.3 V Single-Ended Mode8NETBNETAR110k+3.3 V+5 VRXDTXDGNDVCCINDU

Clock Requirements A Series 6000 chip requires a 10 MHz external crystal or oscillator to provide its input clock signal. The chip then multiplies

Figure 25. Test Point Levels for XIN Duty-Cycle Measurements To ensure proper oscillator startup, the equivalent series resistance specification for

Whenever the documentation for Series 6000 devices describes the system clock rate, it refers to the 10 MHz to 80 MHz internal system clock rate that

In some cases it is desirable to use the input capability of the RST~ pin to allow other devices to reset the Series 6000 device. Examples of extern

• LVI circuit trip • Watchdog timer expiration • System-level traps • Software-driven reset The source of the last reset is saved in the Reset Ca

Watchdog Timer Ticks (840 ms)Update WDTSeries 6000 Chip ResetsUpdate WDT Update WDT No UpdateAbout 840 msFrom Last Update to ResetUpdate WDT Update W

and firmware initialization before executing application programs, including the following tasks: • The ROM system image is copied from ROM to RAM (

Table of Contents Welcome ... iii Audience ...

The state initialization task determines if the external flash needs to be initialized; if it does need to be initialized, the state initialization t

SVC~ Pin The SVC~ pin alternates between input and open-drain output at a 76 Hz rate with a 50% duty cycle. When it is an output, it can sync up t

Device State State Code Service LED Configured, Hard Offline 6 Off Configured 4 Off Defective External Memory — On The SVC~ pin is active low

The application image checksum covers the application code in both the Application Resident Code and Constant Data areas. The default behavior is th

3 Hardware Design Considerations This chapter describes PCB layout guidelines for Series 6000 chips, and describes how to use an FT 6000 Smart Tran

PC Board Layout Guidelines Electrostatic discharge (ESD) and electromagnetic interference (EMI) are two of the most important design considerations

opportunity to run through the Series 6000 chip itself, and any other circuitry, such as a host microprocessor. Transceiver-Side Clamp Diodes: Two d

Variations on this suggested PCB layout are possible as long as the general principles discussed in this chapter are followed. Through-hole capacitor

4 Design and Test for Electromagnetic Compatibility This chapter describes electromagnetic compatibility design considerations for Series 6000 de

Comparison with FT 3120 or FT 3150 Devices ... 55 Comparison with Series 5000 Devices ...

Overview A product that is designed for electromagnetic compatibility (EMC) must be able to pass rigorous tests for immunity to external interference

Achieving High Immunity Achieving good immunity to ESD and other types of network transients requires good layout of the power, ground, and other dev

between electrically charged objects at different voltage potentials (one of which can be ground). The most common form of ESD is an electric spark,

B. The European comité européen de normalisation electrotechnique6 (CENELEC) EN 55022 standard and the international comité international spécial de

As Cleak,SIGNAL increases, a larger current flows during Vgate transitions, and more common-mode RF current couples onto the network twisted pair. T

The EN 61000-4-3 RF Susceptibility test is generally performed in an RF-shielded anechoic chamber with high-power transmitter-driven antennas aimed a

EQUIPMENTUNDERTEST (EUT)HP8656BSIGNALGENERATOR75WPOWERAMPGROUND PLANETESTCONTROLCOMPUTERFCCCDN - M350ΩAUXILIARYEQUIPMENT(AE)Dressler Alpha 250 / 75W-

EQUIPMENTUNDERTEST (EUT)HP8656BSIGNALGENERATOR75WPOWERAMPGROUND PLANETESTCONTROLCOMPUTERFCCCDN - M350ΩAUXILIARYEQUIPMENT(AE)Dressler Alpha 250 / 75W-

There are two levels of network testing that are relevant to Series 6000 devices: • Level 3, which represents a typical industrial environment, inje

connected to a stable Earth ground. Alternatively, two each of two-electrode configurations can be used (contact manufacturer for details). Table 2