Echelon FT 3150 Smart Transceiver Manual de usuario Pagina 116
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Chapter 5 - Network Cabling and Connections
110 FT 3120 / FT 3150 Smart Transceiver Data Book
Network Connection
The network connection (NET1 and NET2) is polarity insensitive. Therefore, either of the two twisted pair wires can
be connected to either of these network connections.
Network Topology Overview
The TP/FT-10 network is designed to support free topology wiring, and will accommodate bus, star, loop, or any
combination of these topologies. LPT-10 Transceiver-based devices and FT 3120 and FT 3150 Smart Transceiver-
based devices can be located at any point along the network wiring. This capability simplifies system installation and
makes it easy to add devices if the network need to be expanded. Figures 5.1 through 5.5 present five different
network topologies. The actual termination circuit will vary by application.
Figure 5.1 Singly Terminated Bus Topology
Figure 5.2 Doubly Terminated Bus Topology
Figure 5.3 Star Topology
Termination
Termination Termination
Termination
- / FT 3150 1
- Smart Transceiver Data Book 1
- Table of Contents 3
- Audience 8
- Product Overview 8
- LONWORKS Device 9
- Chapter 1 - Introduction 10
- Related Documentation 11
- Hardware Resources 13
- Overview 14
- Neuron Processor Architecture 14
- Memory Allocation 19
- • Unique 48-bit Neuron ID 21
- Static RAM 22
- Preprogrammed ROM 22
- Input/Output 23
- Clock Input 24
- Additional Functions 25
- RESET Pin 26
- • Oscillator start-up 28
- • Oscillator stabilization 28
- • SERVICE pin initialization 28
- • State initialization 28
- • Off-chip RAM initialization 29
- • System RAM setup 29
- • Checksum initialization 29
- • Scheduler initialization 30
- SERVICE Pin 33
- Integrity Mechanisms 34
- Reset Processing 36
- Signatures 36
- Interfaces 37
- Hardware Considerations 39
- (200 ns pulse 42
- Input Clock) 42
- I/O Timing Issues 43
- Direct I/O Objects 46
- Byte Input/Output 47
- Figure 3.8 Byte I/O 48
- Leveldetect Input 49
- Nibble Input/Output 50
- Parallel I/O Objects 51
- Parallel Input/Output 52
- Serial I/O Objects 63
- C Input/Output 65
- Magcard Input 66
- Magtrack1 Input 68
- Serial Input/Output 72
- Touch Input/Output 73
- Figure 3.33 Touch I/O Object 74
- Wiegand Input 75
- Timer/Counter Input Objects 76
- Dualslope Input 77
- Edgelog Input 78
- Infrared Input 79
- Ontime Input 80
- Period Input 81
- Reference Figure 3.35 82
- Optional Pull-Up Resistors 82
- Pulsecount Input 83
- Quadrature Input 84
- Totalcount Input 85
- Timer/Counter Output Objects 86
- Frequency Output 87
- Frequency Resolution and 88
- Maximum Range at 10MHz 88
- Oneshot Output 89
- Pulsecount Output 90
- Pulsewidth Output 91
- Triac Output 92
- Triggered Count Output 93
- (Clock Select + n) 95
- Clock Select 96
- Hardware Design 97
- Transceiver 98
- ONWORKS 100
- PC Board Layout Guidelines 101
- Component Side Solder Side 103
- (X -ray view ) 103
- Keep-out area 103
- S tar G round 104
- EMI Design Issues 105
- 3-Terminal Voltage 106
- Regulator 106
- ESD Design Issues 107
- Building Entrance Protection 108
- Network Line Protection 108
- Shield Protection 109
- • Balanced circuits/lines; 111
- Dressler 112
- Alpha 250 / 75W 112
- ATT 6 / 75 112
- FTT-10A Transceiver 114
- FT 31x0 Smart 114
- Transceiver with 114
- C5 = C6 = 56pF caps 114
- Network Cabling and 115
- Connections 115
- Network Connection 116
- Network Topology Overview 116
- Termination 117
- System Specifications 118
- Transmission Specifications 118
- Free Topology Network Segment 119
- Twisted Pair 120
- Termination Circuit 120
- Grounding 120
- Programming 121
- Considerations 121
- NodeBuilder Development Tool 122
- FT Smart Transceiver 125
- Design Checklist 125
- Introduction 126
- Device Checklist 126
- Qualified TP/FT-10 129
- Cable Specifications 129
- Qualified Cables 130
- Design and Handling 133
- Guidelines 133
- Application Considerations 134
- Decoupling Capacitors 137
- Electrostatic Discharge 142
- Recommended Reading 143
- Reference Design 147
- Schematics and Layout 147
- Mini Evaluation Kit Board 148
- FT 3150 Evaluation Board Core 149
- FT Network 150
- Optional Regulators 150
- <Doc> 150
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