Echelon FT 3150 Smart Transceiver Manual de usuario Pagina 3
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FT 3120 / 3150 Smart Tranceiver Data Book i
Table of Contents
Chapter 1 - Introduction ......................................................................................1
Introduction .......................................................................................................2
Audience ...........................................................................................................2
Product Overview .............................................................................................2
Free Topology Technology Overview ..............................................................4
Related Documentation .....................................................................................5
Chapter 2 - Hardware Resources ........................................................................7
Overview ...........................................................................................................8
Neuron Processor Architecture .........................................................................8
Memory Allocation .........................................................................................13
FT 3120 Smart Transceiver ......................................................................13
FT 3150 Smart Transceiver ......................................................................13
EEPROM ..................................................................................................14
Static RAM ...............................................................................................16
Preprogrammed ROM ...............................................................................16
External Memory of the FT 3150 Smart Transceiver ...............................16
Input/Output ...................................................................................................17
Eleven Bidirectional I/O Pins ...................................................................17
Two 16-Bit Timer/Counters ......................................................................17
Clock Input .....................................................................................................18
Clock Generation ......................................................................................18
Additional Functions .......................................................................................19
Reset Function ..........................................................................................19
RESET Pin ................................................................................................20
Power Up Sequence ............................................................................20
Software Controlled Reset ..................................................................21
Watchdog Timer .................................................................................21
LVI Considerations .............................................................................21
Reset Processes and Timing .....................................................................22
SERVICE
Pin ...........................................................................................27
Integrity Mechanisms .....................................................................................28
Memory Integrity Using Checksums ........................................................28
Reboot and Integrity Options Word ..........................................................29
Reset Processing .......................................................................................30
Signatures ..................................................................................................30
Chapter 3 - Input/Output Interfaces ................................................................31
Overview .........................................................................................................32
Hardware Considerations ................................................................................33
I/O Timing Issues ............................................................................................37
Scheduler-Related I/O Timing Information ..............................................38
Firmware and Hardware-Related I/O Timing Information .......................39
- / FT 3150 1
- Smart Transceiver Data Book 1
- Table of Contents 3
- Audience 8
- Product Overview 8
- LONWORKS Device 9
- Chapter 1 - Introduction 10
- Related Documentation 11
- Hardware Resources 13
- Overview 14
- Neuron Processor Architecture 14
- Memory Allocation 19
- • Unique 48-bit Neuron ID 21
- Static RAM 22
- Preprogrammed ROM 22
- Input/Output 23
- Clock Input 24
- Additional Functions 25
- RESET Pin 26
- • Oscillator start-up 28
- • Oscillator stabilization 28
- • SERVICE pin initialization 28
- • State initialization 28
- • Off-chip RAM initialization 29
- • System RAM setup 29
- • Checksum initialization 29
- • Scheduler initialization 30
- SERVICE Pin 33
- Integrity Mechanisms 34
- Reset Processing 36
- Signatures 36
- Interfaces 37
- Hardware Considerations 39
- (200 ns pulse 42
- Input Clock) 42
- I/O Timing Issues 43
- Direct I/O Objects 46
- Byte Input/Output 47
- Figure 3.8 Byte I/O 48
- Leveldetect Input 49
- Nibble Input/Output 50
- Parallel I/O Objects 51
- Parallel Input/Output 52
- Serial I/O Objects 63
- C Input/Output 65
- Magcard Input 66
- Magtrack1 Input 68
- Serial Input/Output 72
- Touch Input/Output 73
- Figure 3.33 Touch I/O Object 74
- Wiegand Input 75
- Timer/Counter Input Objects 76
- Dualslope Input 77
- Edgelog Input 78
- Infrared Input 79
- Ontime Input 80
- Period Input 81
- Reference Figure 3.35 82
- Optional Pull-Up Resistors 82
- Pulsecount Input 83
- Quadrature Input 84
- Totalcount Input 85
- Timer/Counter Output Objects 86
- Frequency Output 87
- Frequency Resolution and 88
- Maximum Range at 10MHz 88
- Oneshot Output 89
- Pulsecount Output 90
- Pulsewidth Output 91
- Triac Output 92
- Triggered Count Output 93
- (Clock Select + n) 95
- Clock Select 96
- Hardware Design 97
- Transceiver 98
- ONWORKS 100
- PC Board Layout Guidelines 101
- Component Side Solder Side 103
- (X -ray view ) 103
- Keep-out area 103
- S tar G round 104
- EMI Design Issues 105
- 3-Terminal Voltage 106
- Regulator 106
- ESD Design Issues 107
- Building Entrance Protection 108
- Network Line Protection 108
- Shield Protection 109
- • Balanced circuits/lines; 111
- Dressler 112
- Alpha 250 / 75W 112
- ATT 6 / 75 112
- FTT-10A Transceiver 114
- FT 31x0 Smart 114
- Transceiver with 114
- C5 = C6 = 56pF caps 114
- Network Cabling and 115
- Connections 115
- Network Connection 116
- Network Topology Overview 116
- Termination 117
- System Specifications 118
- Transmission Specifications 118
- Free Topology Network Segment 119
- Twisted Pair 120
- Termination Circuit 120
- Grounding 120
- Programming 121
- Considerations 121
- NodeBuilder Development Tool 122
- FT Smart Transceiver 125
- Design Checklist 125
- Introduction 126
- Device Checklist 126
- Qualified TP/FT-10 129
- Cable Specifications 129
- Qualified Cables 130
- Design and Handling 133
- Guidelines 133
- Application Considerations 134
- Decoupling Capacitors 137
- Electrostatic Discharge 142
- Recommended Reading 143
- Reference Design 147
- Schematics and Layout 147
- Mini Evaluation Kit Board 148
- FT 3150 Evaluation Board Core 149
- FT Network 150
- Optional Regulators 150
- <Doc> 150
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